Event status register
The event status register bits are set when certain events occur during PLZ-5W operation. All the event status register bits are set by the error event queue.
You can check the error content with SYST:ERR?.
|Bit||Bit weight||Bit name||Description|
|0||1||Operation Complete(OPC)||Set when an *OPC command is received and all operations in standby have been completed.|
|1||2||Request Control (RQC)||Not used|
|2||4||Query Error(QYE)||Set when an attempt is made to read data from the output queue when there is no data or when the output queue is not in the wait state. This indicates that there is no data in the output queue.|
|3||8||Device Dependent Error(DDE)||Set when there is a device-specific error.|
|4||16||Execution Error(EXE)||Set when the PLZ-5W evaluates that the program data after the header is outside the formal input range or does not match the specifications of the PLZ-5W. This indicates that a valid SCPI command may not be executed correctly depending on the state of the PLZ-5W.|
|5||32||Command Error(CME)||Set when an IEEE 488.2 syntax error is detected by the parser, when an unidentifiable header is received, or when a group execution trigger enters the internal IEEE 488.2 SCPI command input buffer.|
|6||64||User Request||Not used|
|7||128||Power ON(PON)||Not used|