Event status register
The event status register bits are set when certain events occur during KFM2150 operation. All bits of the event status register are set by the error event queue.
The register is defined by the IEEE488.2 standard. IEEE488.2 common commands *ESE, *ESE?, and *ESR? are used to control the register.
Table 8 Event status register (Standard Event Status Resister)
|Bit||Bit Weight||Bit Name||Description|
|0||1||Operation Complete (OPC)||Set when an *OPC command is received and all operations in standby are complete.|
|1||2||Request Control (RQC)||Not used|
|2||4||Query Error (QYE)||Set when an attempt is made to read data from the output queue when no output is either present or pending.Indicates that there is no data in the output queue.|
|3||8||Device Dependent Error (DDE)||Set when there is a device-specific error.|
|4||16||Execution Error (EXE)||Set when the KFM2150 evaluates the program data following the header is outside the formal input range or does not match the performance of the KFM2150. This indicates that a valid SCPI command may not be executed correctly depending on the conditions of the KFM2150.|
|5||32||Command Error (CME)||Set when an IEEE 488.2 syntax error is detected, when an unidentifiable header is received, or when a group execution trigger enters the internal IEEE 488.2 SCPI command input buffer.|
|6||64||User Request (URQ)||Not used|
|7||128||Power ON (PON)||Not used|